This application is based on Japanese Patent application Nos. 2000-203886 and 2000-262901, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an apparatus and method of correcting a pattern skew caused in a pattern forming process such as optical lithography and etching to be utilized for manufacturing a semiconductor device, and a method of manufacturing a semiconductor device using the correction.
2. Description of the Related Art
At present, the design rule of a semiconductor device reaches a level of 0.15 xcexcm and this level is smaller than a wavelength (ex. 0.248 xcexcm for KrF excimer laser) of a light source of a stepper for transcription. In such a situation, a resolution characteristic is extremely deteriorated, and therefore a special lithography technology such as a modified illuminating technology is used to improve the resolution.
Even though the resolution characteristic is improved by using this special lithography technology, the fidelity of a pattern is deteriorated. Moreover, since a pattern becomes minute also in another process such as an etching process, a fluctuation of the dimension of the pattern occurs due to density difference of the pattern.
In order to deal with these problems, an OPC (Optical Proximity Effect Correction) technology which modifies a design layout pattern to obtain a desired pattern is widely used. There exist three kinds of OPC methods including a model based OPC, a rule based OPC and a combination of these two OPC methods. The model based OPC modifies a pattern based on a result of simulation. The rule based OPC specifies a specification (OPC rule) to modify a design layout pattern, taking into account phenomenal features (widths of respective patterns, a distance between adjacent patterns, a distance from a corner portion) of the design layout pattern, and then modifies the design layout pattern based on this rule.
As the pattern becomes minute, more complicated OPC process is to be required, and thus output pattern data after OPC become complicated polygonal. For this reason, a lot of figures having very small protrusions, notches or steps shape are generated in the output pattern data after OPC. Such a lot of figures including protrusion figures, notch-shaped figures or step-shaped figures increases a number of vertices of the figures, resulting in a problem of data amount to be increased.
FIG. 11 shows the layout pattern data after the OPC process. In FIG. 11, patterns represented by broken lines are those before the OPC process. A pattern C1 is a pattern applied by the OPC process. Patterns of protrusion 13 and 15, notches 11, 14 and 16, and steps 12, 17 and 18 are added to the patterns before the OPC process. Even if such very small protrusive, notch-shaped or step-shaped patterns are deleted, there arises no optical problem.
A method of deleting very small protrusions and notches generated after the conventional OPC will be explained below. There exist two kinds of methods of deleting protrusions and notches. One of them is a method using spacing check to be used in a design rule check (DRC) tool, and the other is a method using sizing process. There will be explained below these methods.
First, the deleting method using spacing check will be explained.
FIG. 12A shows an example of a protrusion which is generated in the OPC process. In the case where this protrusion is deleted, a protrusion deletion-use figure C is generated on a portion of which width is W or less by the DRC tool as shown in FIG. 12B. The figure C is subtracted (NOT operation) from the original layout data so that the protrusion figure is deleted (see FIG. 12C). The similar manner is applied for the notch-shaped figure. The notch figure can be deleted by generating a notch deletion-use figure using a gap of the figures and adding (OR operation) this figure to the original pattern. FIG. 14A shows a result of reducing or deleting the protrusion figures and notch figures from the pattern shown in FIG. 11 in this method. As shown in the drawing, the notch FIGS. 11 and 14 and the protrusion FIG. 15 are deleted.
However, this method cannot delete protrusion and notch figures such as patterns 13 and 16. This is because in theses figures each side composing the respective figure does not have a side in a opposed side, and thus the width and gap of these figures are judged as large, and deletion-use figures cannot be generated.
There will be explained the deleting method using sizing process.
FIG. 13A shows an example of the notch generated in the OPC process. In the case where this notch is deleted, executed are over-sizing process and under-sizing process with xc2xd of a width S of a notch figure N to be deleted. FIG. 13B shows a figure after the over-sizing process. The notch with the width S or less is buried by the over-sizing process. Thereafter, the under-sizing process is executed so that layout data pattern shown in FIG. 13C in which the notch figure has been deleted can be obtained. Similarly, the protrusion figure can be deleted by the over-sizing process after the under-sizing process. FIG. 14B shows a result that the protrusion and notch figures are deleted from the data pattern shown in FIG. 11 by this method. As shown in the diagram, the notch FIGS. 11, 14 and 16 are deleted.
In such the deleting methods using the sizing processes, there is a problem in which acute figures such as patterns 24 and 25 are generated depending on a sizing amount, due to the under-sizing and over-sizing processes for protrusion figures having inclined lines or the over-sizing and under-sizing processes for notch figures having inclined lines. When a sizing amount is increased in order to avoid this generation, for deletion of the protrusion figures, pattern would disappear due to the under-sizing process, and for deletion of the notch figures, gaps between adjacent patterns would be filled by the over-sizing process. As a result, arbitrary protrusion figures and notch figures cannot be deleted.
Further, step patterns such as patterns 12, 17 and 18 shown in FIG. 11 cannot be deleted by the above-mentioned methods using spacing check and sizing.
Therefore, even if the spacing check or sizing process is used, there is a lot of figures of multiple-vertices having plural protrusions, notches and steps exist which are not able to be deleted. Thus, there is a problem in which a data amount after the OPC process increases.
The present invention is devised in order to solve the above problems, and it is an object of the present invention to provide an apparatus and method of correcting layout pattern, which can reduce protrusive regions, notch-shaped regions and step-shaped regions from design layout patterns in manufacturing a semiconductor device to reduce a data amount of the layout patterns.
In a first aspect of the invention, an apparatus of correcting layout pattern data comprises a side extracting section for extracting sides composing a region to be deleted having a predetermined shape in a layout pattern of a circuit, a deletion-use pattern generator for generating a deletion-use pattern which is used to delete the region to be deleted, based on the extracted sides, and an operation section for executing a predetermined operation to the layout pattern with the deletion-use pattern to remove the region to be deleted from the original layout pattern.
The side extracting section may extract four sides from the layout pattern. The first side has a predetermined length. The second side has a predetermined length longer than the first side and forms a predetermined angle with the first side. The third side is adjacent to the first side and forms a predetermined angle with the first side. The fourth side is adjacent to the second side and forms a predetermined angle with the second side.
The deletion-use pattern generator may determine an intersectional point of a first straight line with a second straight line, and generate, using the intersectional point, the deletion-use pattern to delete a protrusion or notch region. The first straight line extends parallel with the first side and passing through an end of the third side spaced from the first side. The second straight line extends parallel with the second side and passing through an end of the fourth side spaced from the second side.
The deletion-use pattern generator may determine an intersectional point of a straight line which extends parallel with the second side and passes through an end of the third side contacting with the first side, and an extended line of the fourth side, and generate using the intersectional point the deletion-use pattern for deleting a step shaped region.
When the each side of the pattern is specified according to coordinate on a predetermined grid, and if the intersectional point is not localized on the grid, one point on the grid may be selected so that a difference in layout pattern shapes becomes minimum between before and after deleting the region to be deleted, and the coordinate of the intersectional point may be localized on the selected point on the grid.
In a second aspect of the invention, a method of correcting layout pattern data comprises extracting sides composing a region to be deleted having a predetermined shape in a layout pattern of a circuit, generating a deletion-use pattern which is used to delete the region to be deleted, based on the extracted sides, and executing a predetermined operation to the layout pattern with the deletion-use pattern to remove the region to be deleted from the original layout pattern.
In a third aspect of the invention, an information recording medium stores a program for controlling an apparatus of correcting a layout pattern of a circuit. The program makes the apparatus execute the following functions. The functions comprises a side extracting function for extracting sides composing a region to be deleted having a predetermined shape in a layout pattern of a circuit, a deletion-use pattern generating function for generating a deletion-use pattern which is used to delete the region to be deleted, based on the extracted sides, and a figure operation function for executing a predetermined operation to the layout pattern with the deletion-use pattern to remove the region to be deleted from the original layout pattern.
According to the invention, protrusion regions, notch regions and step regions can be specified in a simple process to remove those regions from the layout pattern. Therefore, since patterns such as protrusions, notches and steps in a layout pattern can be removed from a layout pattern in a simple process, pattern data with less number of vertices can be obtained, and thus increase of data amount of a compensated layout pattern can be suppressed.